The ALICE data-acquisition system will use more than 400 optical links DDL (DDL) to transfer the data from the detector electronics directly into the PC memory through a PCI adapter: the Read-out Receiver Card (RORC). Two types of RORC had been developed: the 32-bit 33 MHz pRORC and the 64-bit 66 and 100 MHz D-RORC.

The pRORC is a PCI based Read-out Receiver Card developed for the ALICE DDL project by KFKI-RMKI Budapest, Technical University Budapest and CERN.

It is a simple 33 MHz 32 bit PCI card which interfaces the DDL (Detector Datat Link) to the PCI bus. The pRORC card can be used as a PCI master during data collection and as a stand-alone PCI data source.

Its working principle can be see in Figure 1. During data collection a so called Free FIFO has to continuously be loaded by the addresses of the memory blocks (so called pages) where the data has to be written to. The Free FIFO is a 64 bit wide FIFO located on the pRORC card containing the following information:

• Start address of the memory page where the next data page can be loaded (32 bits).
• Size of the given page (24 bits).
• Index of the Ready FIFO where information should be loaded at the end of the transfer (8 bits).

The Ready FIFO is a 64 bit wide software area. After a successful data transfer it contains:

• The length of the data loaded into the corresponding memory page (32 bits).
• The transfer status (32 bits). If the given page was the last page of an event-block then this field contains the Data Transmission Status Word (DTSW), which is added to the event-block according to the DDL protocol. For other (not event-block ending) pages this field is loaded with 0. The DTSW can contain a continuation bit, which signals that the next event block belongs to the same event.

The D-RORC (DAQ Read-out Receiver Card) is a PCI based RORC developed for the ALICE DDL project by KFKI-RMKI Budapest and CERN. The two DDL interfaces integrated on the card can either receive detector data, or copy and transfer them to the High-Level Trigger system. Using the 64-bit PCI interface core, the D-RORC offers more than 400 MB/s bandwidth.

The hardware is built around a programmable logic device from ALTERA. The DIU ports are implemented by the on-board electrical and optical transceivers. In addition, the card contains a CMC compatible feature-extension interface. The D-RORC is 64-bit/66 or 100 MHz PCI or PCI-X compliant, which is achieved by using an intellectual property (IP) core from PLDA. General purpose LVDS ports are available for generating the busy signal of a detector.

The firmware is responsible for the autonomous, bi-directional data transfer between the DIU ports and host memory through the PCI local bus. Each channel consists of three blocks: a) a receiver channel that performs master mode DMA write to the PC memory; b) a transmitter channel that performs master mode DMA read from the PC memory; c) a DIU interface that manages the DDL protocol. The transactions on the local bus are managed by the PCI IP core. The DMA t ransfer eliminates the need of on-board memory and reduces the software overhead.

The integrated DIU interfaces can be used in two different ways. For detectors that do not require high-level trigger (HLT) processing, the DIUs will be connected to the front-end electronics via the Source Interface Unit (SIU). If the HLT system is used, the D-RORC will play the role of a splitter. The raw data received on its first DIU port will be copied and transferred to the HLT farm using the second DIU port working as an SIU. The D-RORC supports system-level testing using the built-in data generator, which can produce formatted data blocks that can be sent over either the PCI or the DDL. More advanced tests including the ALICE Trigger System can be done using the DDL Data Generator (DDG). The DDG is based on the D-RORC and uses its facilities (i.e. the CMC interface and the DMA engines) to generate realistic detector events.

The working principle of the software can be see in Figure 1. During data collection a so called Free FIFO has to continuously be loaded by the addresses of the memory blocks (so called pages) where the data has to be written to. The Free FIFO is a 64 bit wide FIFO located on the D-RORC card containing the following information:

• Start address of the memory page where the next data page can be loaded (32 bits).
• Size of the given page (24 bits).
• Index of the Ready FIFO where information should be loaded at the end of the transfer (8 bits).

The Ready FIFO is a 64 bit wide software area. After a successful data transfer it contains:

• The length of the data loaded into the corresponding memory page (32 bits).
• The transfer status (32 bits). If the given page was the last page of an event-block then this field contains the Data Transmission Status Word (DTSW), which is added to the event-block according to the DDL protocol. For other (not event-block ending) pages this field is loaded with 0. The DTSW can contain a continuation bit, which signals that the next event block belongs to the same event.

A software library has been developped to operate the D-RORC. It is documented in several RORC software documents. The programs and routines described in these documents work under CERN Scientific LINUX (SLC) operating system. Currently we have RORC driver for SLC3, (kernel version 2.4) and SLC4 (kernel version 2.6). The RORC software supports only 32 bit machines.

The first version of the D-RORC has been designed and manufactured. It has been tested extensively in the laboratory using the ALICE data-acquisition software, called DATE. Performance measurements show that the card copes easily with two DDLs conveying data blocks at a transfer rate of 400 MB/s. The D-RORC is going to be used by detector groups in their laboratories and during test beam activities.