The
ALICE detector data link (DDL) interfaces the front-end electronics (FEE) of all the sub-detectors to the read-out receiver cards (RORC) of the data-acquisition system (DAQ). The DDL source interface units (SIU) are connected to the FEEs and placed inside the detector. The DDL destination interface units (DIU) are connected to the RORCs, located in the counting room about 200 meters from the detector. The two DDL interface units are connected through two multi-mode optical fibres. The complete
ALICE DAQ system will contain of about 400 DDLs.
The main data flow takes place from the FEE to the RORC. The 400 DDLs transmit in total 2.5 GB/s event data from the FEE to the RORC with a dead-time of less than 10%. Each DDL is able to transmit data at a rate of 200 MB/s with a detected bit error rate of less than 10-15. As the zero suppression algorithm requires downloading blocks of data into the FEE, high-speed data transmission is also possible in the opposite direction.
Some of the ALICE subsystems (e.g. muon trigger) requires high-speed bidirectional information transfer between VME crates. The DDL also supports this working mode, using a DIU and a RORC at the both end of the link.
Both the FEE and the SIU shall be remotely controlled by the RORC through the DDL, since their placement inside the detector will not allow using any other cabling apart from the DDL medium. Therefore, commands and status information shall also be transmitted between the FEE and the RORC.
To achieve the high reliability of the experimental apparatus, efficient test of all the sub-systems should be provided. The DDL itself also have a powerful built-in self-test (BIST) mode.
At the first prototype version 2 DIUs were connected to the
VME based RORC. For each DDL channel the VME based RORC has a 1 MB
output buffer for the outgoing data blocks and a 2 MB dual-port input buffer for the event data.
The
PCI based RORC (pRORC and D-RORC) interfaces the DDL to the PCI bus. pRORC is a 33 MHz 32 bits, while D-RORC is a 66 or 100 MHz 64 bits PCI master card which can be used as data collecting device and standalone PCI data source.
The performance, the protocol and the bit
error rate of the complete DDL read-out chain from FEE to PC
has been tested.